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英语翻译TheAddressBus1.Thebusmastercontrollingthedatatransfermustthereforebeabletoprovideanaddressforthedata.Mostcomputersystemsprovideanexplicitaddressbusthatoperatesinparallelwiththedatabus.Somesystemscombine
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英语翻译
The Address Bus
1.The bus master controlling the data transfer must therefore be able to provide an address for the data.
Most computer systems provide an explicit address bus that operates in parallel with the data bus.
Some systems combine the address and data buses together into a single multiplexed address/data bus.
This type of bus is said to be time-division multiplexed because time is divided into address slots and data slots
2.The Address Bus
Figure given below describes the multiplexed address/data bus which is cheaper to implement than conventional non-multiplexed buses because it requires fewer signal paths,and the connectors and sockets are cheaper since they require fewer pins.The efficiency of both non-multiplexed and multiplexed address buses can be improved by operating them in a burst mode and this mode operation is used to support cache memory systems.
3.The Control Bus
The control bus is responsible for regulating the flow of information on the data bus.
The simplest control bus requires two signals:a data-direction signal and a data-validation signal
The data direction (R/W* ) signal is high to indicate a read operation and low to indicate a write operation
4.The active-low data valid signal,DAV*,is asserted by the bus master to indicate that a data transfer is taking place.
The bus master controls the data transfer with DAV* and the bus slave must complete the data transfer within the time allocated.
Figure below provides the timing diagram of a generic synchronous read cycle.
5.Asynchronous Data Transfer
An asynchronous bus cycle uses a two-way communication with the slave called a handshake
An asynchronous data transfer requires three control signals:R/W*,DAV*,and DAC* (data acknowledge).
The new signal,DAC*,is the response from the bus slave indicating that the data transfer may be completed.
抱歉,那翻译后2段好了,我好像太残忍了
The Address Bus
1.The bus master controlling the data transfer must therefore be able to provide an address for the data.
Most computer systems provide an explicit address bus that operates in parallel with the data bus.
Some systems combine the address and data buses together into a single multiplexed address/data bus.
This type of bus is said to be time-division multiplexed because time is divided into address slots and data slots
2.The Address Bus
Figure given below describes the multiplexed address/data bus which is cheaper to implement than conventional non-multiplexed buses because it requires fewer signal paths,and the connectors and sockets are cheaper since they require fewer pins.The efficiency of both non-multiplexed and multiplexed address buses can be improved by operating them in a burst mode and this mode operation is used to support cache memory systems.
3.The Control Bus
The control bus is responsible for regulating the flow of information on the data bus.
The simplest control bus requires two signals:a data-direction signal and a data-validation signal
The data direction (R/W* ) signal is high to indicate a read operation and low to indicate a write operation
4.The active-low data valid signal,DAV*,is asserted by the bus master to indicate that a data transfer is taking place.
The bus master controls the data transfer with DAV* and the bus slave must complete the data transfer within the time allocated.
Figure below provides the timing diagram of a generic synchronous read cycle.
5.Asynchronous Data Transfer
An asynchronous bus cycle uses a two-way communication with the slave called a handshake
An asynchronous data transfer requires three control signals:R/W*,DAV*,and DAC* (data acknowledge).
The new signal,DAC*,is the response from the bus slave indicating that the data transfer may be completed.
抱歉,那翻译后2段好了,我好像太残忍了
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答案和解析
好多计算机方面的术语,是关于总线和端口数据传送方面的,翻译太吃力了.
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