VHDLlibraryieee;useieee.std_logic_1164.all;entityweisport(A,B,C,D:inbit;g,f,e,d,c,b,a:outbit);endwe;architectureqwe1ofweissignalcomb:bit_vector(3downto0);signaltemp:bit_vector(6downto0);begincombtemptemptemptemptemptemptemptemptemp

Question

VHDL
library ieee;
use ieee.std_logic_1164.all;
entity we is
port(A,B,C,D:in bit;
g,f,e,d,c,b,a:out bit);
end we;
architecture qwe1 of we is
signal comb:bit_vector(3 downto 0);
signal temp:bit_vector(6 downto 0);
begin
combtemptemptemptemptemptemptemptemptemptemptemp

Answer 1

VHDL不区分大小写,输入端口中的A、B、C、D与输出端口中的a、b、c、d重名了,将输入端口的A、B、C、D改为A_in、B_in、C_in、D_in就可以.