,我有2个VHDL源程序调试不出来.libraryieee;useieee.stdlogic1164.all;useieee.stdlogicarith.all;useieee.stdlogicunsigned.all;entitysmultadd1isport(clkregbt,clkreg:instdlogic;a0,a1,a2,b0,b1,x0,x1,x2:instdlogicvector(4downt

Question

,我有2个VHDL源程序调试不出来.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity smultadd1 is
port (clk_regbt,clk_reg:in std_logic;
a0,a1,a2,b0,b1,x0,x1,x2:in std_logic_vector(4 downto 0);
y0,y1:in std_logic_vector(8 downto 0);
yout:out std_logic_vector(8 downto 0));
end smultadd1;
architecture bhv of smultadd1 is
signal tan,tbn,tp2n:std_logic;
signal cnt:std_logic_vector(2 downto 0);
signal ta,tb,taa,tbb:std_logic_vector(3 downto 0);
signal tmpa,tmpb:std_logic_vector(4 downto 0);
signal tp,tpp,tppp:std_logic_vector(7 downto 0);
signal ytmp,p:std_logic_vector(8 downto 0);
begin
tmpa'0');
tmpb'0');
ta

Answer 1

tmpb'0');
这里有问题吧
tmpb:std_logic_vector(4 downto 0);
y0,y1:in std_logic_vector(8 downto 0);
tmpb和y0、y1信号的位数不一样