VHDL中出现以下错误是什么原因ELSECLAUSEFOLLOWINGCLOCKEDGEMUSTHOLDTHESTATEOFSIGNAL以下是源程序LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;USEIEEE.STDLOGICUNSIGNED.ALL;ENTITYKUOPIN1ISPORT(EN,CLK,SIN:INSTDLOGIC;SIGOUT:OUT

Question

VHDL中出现以下错误是什么原因ELSE CLAUSE FOLLOWING CLOCK EDGE MUST HOLD THE STATE OF SIGNAL
以下是源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KUOPIN1 IS
PORT(EN,CLK,SIN:IN STD_LOGIC;
SIG_OUT:OUT STD_LOGIC);
END;
ARCHITECTURE ONE OF KUOPIN1 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(62 DOWNTO 0);
BEGIN
PROCESS(EN,SIN)
CONSTANT PN63:STD_LOGIC_VECTOR(62 DOWNTO
0):="110010010101001101000010001011011111101011100011001110110000011";
CONSTANT PN63_NOT:STD_LOGIC_VECTOR(62 DOWNTO
0):="001101101010110010111101110100100000010100011100110001001111100";
VARIABLE TEMP1:STD_LOGIC_VECTOR(62 DOWNTO 0);
BEGIN
IF EN='1' THEN
TEMP1:=(OTHERS=>'0');
ELSE
IF SIN='1' THEN
TEMP1:=PN63_NOT;
ELSE
TEMP1:=PN63;
END IF;
TEMP

Answer 1

一个if就要对应一个end if
或者你不想写end if 就要把else 和if连起来写成elsif,这样只要写一个end if就行了.
还有一些其他错误,已改好且编译通过
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KUOPIN1 IS
PORT(EN,CLK,SIN:IN STD_LOGIC;
SIG_OUT:OUT STD_LOGIC);
END KUOPIN1;
ARCHITECTURE ONE OF KUOPIN1 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(62 DOWNTO 0);
BEGIN
PROCESS(EN,SIN)
CONSTANT PN63:STD_LOGIC_VECTOR(62 DOWNTO 0):="110010010101001101000010001011011111101011100011001110110000011";
CONSTANT PN63_NOT:STD_LOGIC_VECTOR(62 DOWNTO 0):="001101101010110010111101110100100000010100011100110001001111100";
VARIABLE TEMP1:STD_LOGIC_VECTOR(62 DOWNTO 0);
BEGIN
IF EN='1' THEN
TEMP1:=(OTHERS=>'0');
ELSE
IF SIN='1' THEN
TEMP1:=PN63_NOT;
ELSE
TEMP1:=PN63;
END IF;
TEMP