VHDL四舍五入判别电路,输入为8421BCD码,请大神帮我看看程序问题在哪里libraryieee;useieee.stdlogic1164.all;entityroundisport(D0,D1,D2,D3:instdlogic;E:inbit;g,r:outbit);endround;architectureoneOFroundISsignalabc:s

Question

VHDL四舍五入判别电路,输入为8421 BCD码,请大神帮我看看程序问题在哪里
library ieee;
use ieee.std_logic_1164.all;
entity round is
port(D0,D1,D2,D3:in std_logic;
E:in bit;
g,r:out bit);
end round;
architecture one OF round IS
signal abc:std_logic_vector(3 DOWNTO 0);
PROCESS(E,D0,D1,D2,D3)
BEGIN
IF E

Answer 1

在实体声明之前再加上一句use  ieee.std_logic_unsigned.all;

将signal abc: std_logic_vector(3 DOWNTO 0);改成variable abc: std_logic_vector(3 DOWNTO 0);并将其放到process(E,D0,D1,D2,D3)的后面；

在进程开始的地方加上一句abc := D3&D2&D1&D0;

IF E<='0' THEN这一句不对,估计是IF E='0' THEN

将case语句改成if语句：if abc<5 then g<='1',r='0'; else g<='0',r='1'; end if;也可以将这个if语句与前面的if语句嵌套成一个if语句：IF E='0' THEN r<='0',g<='0'; elsif abc<5 then g<='1',r='0'; else g<='0',r='1'; end if;