VHDL编程,出现ProcessStatementcannotcontainbothasensitivitylistandaWaitStatement错误代码如下：LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;USEIEEE.STDLOGICUNSIGNED.ALL;ENTITYLIFTISPORT(CLK:INSTDLOGIC;UA,DA,FF,SF,OA,CA:INSTD

Question

VHDL编程,出现Process Statement cannot contain both a sensitivity list and a Wait Statement错误
代码如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LIFT IS
PORT
(
CLK:IN STD_LOGIC;
UA,DA,FF,SF,OA,CA:IN STD_LOGIC;
UPS,DOS,FOS,FCS,SOS,SCS:INOUT STD_LOGIC
--STATE :INOUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END LIFT;
ARCHITECTURE RUN OF LIFT IS
SIGNAL STATE :STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
p1:PROCESS(UA,DA,FF,SF,OA,CA) --提示的错误所在行
BEGIN
CASE STATE IS
WHEN "000"=>
IF(UA= '1')OR(OA= '1') THEN
STATE

Answer 1

PROCESS(UA,DA,FF,SF,OA,CA) --提示的错误所在行
和
WAIT UNTIL STATE < "100";--wait until 和process的敏感表不能一起用.