quartus中VHDL错误libraryieee;useieee.std_logic_1164.all;entityand2is--generic(rise,fall:TIME);port(a,b:inbit;c:outbit);endentity;architecturewenofand2isbeginprocessbeginc

Question

quartus 中VHDL错误
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
-- generic(rise,fall:TIME);
port(a,b:in bit;
c:out bit);
end entity;
architecture wen of and2 is
begin
process
begin
c

Answer 1

小错误 ,检查你的实体名与文件名是否一致,entity .. architecture 里的实体名是否一致!