PROTELProtelDesignSystemDesignRuleCheckPCBFile:JIUSHITA.PCBDate:3-Jan-2011Time:22:01:23ProcessingRule:HoleSizeConstraint(Min=0.0254mm)(Max=2.54mm)(Ontheboard)RuleViolations:0ProcessingRule:WidthConstraint(Min=1mm)(Max=2mm)

Question

PROTEL
Protel Design System Design Rule Check
PCB File :JIUSHITA.PCB
Date :3-Jan-2011
Time :22:01:23
Processing Rule :Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board )
Rule Violations :0
Processing Rule :Width Constraint (Min=1mm) (Max=2mm) (Prefered=1.2mm) (Is part of net class SIGNAL )
Rule Violations :0
Processing Rule :Clearance Constraint (Gap=0.254mm) (On the board ),(On the board )
Violation between Pad W1-3(1184.148mm,1357.884mm) MultiLayer and
Track (1185.672mm,1325.118mm)(1185.672mm,1359.154mm) BottomLayer
Rule Violations :1
Processing Rule :Broken-Net Constraint ( (On the board ) )
Violation Net GND is broken into 2 sub-nets.Routed To 95.00%
Subnet :Q1-3 C1-1 J3-2 C2-1 R7-1 JP1-4 S4-4 U1-20 S4-1 S3-4
S3-1 S2-4 S2-1 S1-4 S1-1 J1-1 W1-1 J4-1
Subnet :J1-20
Violation Net VCC is broken into 2 sub-nets.Routed To 95.00%
Subnet :JP1-1 S5-1 S5-4 D5-1 D6-1 D4-1 D3-1 LS1-2 D2-1 C3-1
D1-1 J2-1 J4-2 U1-40 W1-2 U1-31 J1-19 J1-17
Subnet :J1-2
Rule Violations :2
Processing Rule :Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Violation between Pad JP1-8(967.232mm,1295.908mm) MultiLayer and
Track (967.232mm,1295.908mm)(969.772mm,1298.448mm) BottomLayer
Rule Violations :1
Violations Detected :4
Time Elapsed :00:00:00

Answer 1

Hole Size 孔径超过规则的最大值
Width Constraint线宽规则问题
Clearance Constraint 间距问题
Net GND 布线没有布完GND的信号
Net VCC 布线没有布完vcc的信号
Short-Circuit Constraint 线路短路