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计算机体系结构若干题目(1)1.Asuperscalarprocessorhas()(a)multiplefunctionalunits(b)ahighclockspeed(c)alargeamountofRAM(d)manyI/Oports2.On-chipcachehas()(a)loweraccesstimethanRAM(b)largercapacitythano

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计算机体系结构 若干题目(1)
1.A superscalar processor has ( )
(a)multiple functional units (b) a high clock speed
(c)a large amount of RAM (d) many I/O ports
2.On-chip cache has ( )
(a) lower access time than RAM (b) larger capacity than off chip cache
(c) its own data bus (d) become obsolete
3.( ) data hazards are not possible in the DLX in-order instruction issue and in-order execution multicycle pipeline?
(a) WAR\x05 (b) WAW (c) RAW (d) RAR
4.Pipelining improves CPU performance due to ( )
(a) reduced memory access time (b) increased clock speed
(c) the introduction of parallellism (d) additional functional units
5.Cache memory enhances ( )
(a) memory capacity (b) memory access time
(c) secondary storage capacity (d) secondary storage access time
6.RISC machines typically ( )
(a) have high capacity on-chip cache memories (b) have fewer registers than CISC machines (c) are less reliable than CISC machines (d) execute 1 instruction per clock cycle.
7.Which of the following is NOT a computer performance metric:( )
(a) MIPS (b) FLOPS (c) SPECbenchmark (d) RISC
8.Given a 5 stage pipeline with stages taking 1,2,3,1,1 units of time,the clock period of the pipeline is:( )
(a) 8 (b) 1/8 (c) 1/3 (d) 3
9.The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10ns and the memory access time is 100ns is ( )
(a) 55ns (b) 45ns (c) 90ns (d) 19ns
10.Delayed branching is used ( )
(a) to introduce delays in program execution (b) in pipelining
(c) in cache memory (d) decoding instructions
Part2—Fundamentals of Computer Design [10 points]
1.[10 points] In many practical applications that demand a real-time response,the computational workload W is often fixed.As the number of processors increases in a parallel computer,the fixed workload is distributed to more processors for parallel execution.Assume 20 percent of W must be executed sequentially,and 80 percent can be executed by 4 nodes simultaneously.What is a fixed-load speedup?
Part 3—Instruction Set Architecture [20 points]
2.[8 points] Suppose the variable x of type int and at address 0x100 has a hexadecimal value 0x01234567.The ordering of the bytes within the address range 0x100 through 0x103 depends on the type of machine.What will be arranged in memory 0x100~0x103 according to Little Endian and Big Endian?
3.[12 points] A model machine has 7 instructions,which frequencies are 43%,21%,12%,8%,6%,6%,and 4% respectively.
3.1Encoding operator with the minimum average code length.
3.2According to 5.1,give the value of the minimum average code length.
最好能加一些中文注释
6.[8 points] For two-level branch prediction strategy with (2,2) predictor,how many bits does the branch prediction buffer need for 2K branch instructions?
Part 5—Memory Hierarchy [25points]
7.[7 points] Cache design:Give short answers to the following questions.
7.1Cache miss rates decrease with larger cache block sizes due to what kind of locality?
7.2How many sets in fully associative cache with 64 cache blocks?
7.3How many sets in a direct-mapped cache with 128 cache blocks?
7.4How to keep the main memory and the cache consistent?
8.[18 points] Assume a four blocks direct-mapped cache,two words per block,LRU replacement.The cache is initially empty.For the word address reference stream (reads):
0,1,12,2,3,4,12,5
8.1How many of these eight references are hits?
8.2.If the cache is fully associative instead,how many word address references would be hits?
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